Hardware support: New Rocket Lake benchmarks appear showing decent gains over Comet Lake |
- New Rocket Lake benchmarks appear showing decent gains over Comet Lake
- As feature sizes decrease, combinational logic soft errors are becoming non-negligible, so has there been any deliberate implementation of soft error correction, specifically for combinational logic circuits, or for single latches/registers, in any consumer-level product, like a CPU/microcontroller?
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- Question about a hybrid implementation of xCloud and the Series X's hardware.
- [Der8auer] I found a Custom Loop for ONLY 70€. Can this even be good?
- Starlink Teardown and Analysis
| New Rocket Lake benchmarks appear showing decent gains over Comet Lake Posted: 13 Dec 2020 07:43 PM PST GPU Benchmark - Ashes of the Singularity I know it's Ashes of the Singularity. . .We should be getting more drips and drabs in the coming weeks as we get closer to Rocket Lake launch. I really hope Intel offers cutthroat pricing on these to put overall downward pressure on desktop CPU prices. If GPU supply catches up with demand next year, it could be a fun spring/summer to build a PC. [link] [comments] |
| Posted: 13 Dec 2020 09:20 AM PST It is well known that many error detection, mitigation, and correction methods, such as parity or ECC, have been available in large memory banks, like for RAM for decades now, and even in CPU caches and sometimes parts of state machines. These are mostly large implementations of sequential logic where single event upsets from cosmic rays have a significant enough chance of causing a lasting bit flip, due to the smaller feature size, density, number of latches, etc. Throughout most of computer history, the combinational logic of the CPU, or small sequential logic like singular latches or registers, have remained unprotected. This is mostly due to the unintentional electrical, logical, and temporal masking effects that are due to the low transistor count, number of logic gates, size of transistors, etc., which has made combinational logic soft errors due to SEUs mostly negligible. Over the past few years, the reduced feature size has become a large concern because it may be making combinational logic errors common enough to be a real problem, so I was wondering if there have been any significant implementations of soft error mitigation or correction in combinational logic circuits or single latches/registers in any consumer-level product, like a CPU or microcontroller? Thank you! [link] [comments] |
| Lenovo Legion Y27q-20 Monitor Review Posted: 13 Dec 2020 08:57 PM PST |
| [LTT] How to build a PC without getting RIPPED OFF! (LTT Holiday Build Guide) Posted: 13 Dec 2020 02:17 PM PST |
| Question about a hybrid implementation of xCloud and the Series X's hardware. Posted: 13 Dec 2020 04:37 PM PST If xCloud gaming on the Series X was implemented then, theoretically would that free up the hardware on the Series X to be used for other things? For example, could a hybrid of xCloud and the Series X hardware be used to further amplify visuals together? I picture xCloud streaming in all the necessary game data to achieve admirable visual fidelity but then the Series X hardware is taking it a step further - such as, taking full use of its shader cores to implement AMD's Super Resolution solution. Is this even possible? Or is there a fundamental bandwidth limitation to this? [link] [comments] |
| [Der8auer] I found a Custom Loop for ONLY 70€. Can this even be good? Posted: 13 Dec 2020 08:06 AM PST |
| Starlink Teardown and Analysis Posted: 13 Dec 2020 12:21 PM PST |
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