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    Tuesday, September 15, 2020

    Home Unlabelled Hardware support: [VideoCardz] AMD showcases Radeon RX 6000 graphics card design

    Hardware support: [VideoCardz] AMD showcases Radeon RX 6000 graphics card design

    September 15, 2020

    Hardware support: [VideoCardz] AMD showcases Radeon RX 6000 graphics card design

    [VideoCardz] AMD showcases Radeon RX 6000 graphics card design

    Posted: 14 Sep 2020 02:19 PM PDT

    Sony cuts PS5 production by 4m units due to production yield issues with SoC (Bloomberg Japan article in Japanese; translated info in the comments)

    Posted: 14 Sep 2020 06:48 PM PDT

    Private data gone public: Razer leaks 100,000+ gamers’ personal info

    Posted: 14 Sep 2020 07:12 AM PDT

    Microsoft's underwater data center resurfaces after two years

    Posted: 14 Sep 2020 02:42 PM PDT

    Microsoft declares its underwater data center test was a success

    Posted: 14 Sep 2020 05:12 PM PDT

    [VideoCardz] Intel Xe-HPG graphics cards rumored to offer up to 960 EUs

    Posted: 15 Sep 2020 01:05 AM PDT

    (Buildzoid/AHOC)Rambling about the RX 6000 heatsink

    Posted: 14 Sep 2020 03:54 PM PDT

    New RISCV (Vector) architecture and RISCV-based PC TBA

    Posted: 14 Sep 2020 01:02 PM PDT

    Dell to Trim Workforce This Week in Move to Stay Competitive

    Posted: 14 Sep 2020 04:42 PM PDT

    Intel DG2 discrete graphics spotted with 6GB and 8GB GDDR6 memory - VideoCardz.com

    Posted: 15 Sep 2020 02:24 AM PDT

    How tightly coupled are uarch cores and ISA front-ends?

    Posted: 14 Sep 2020 08:56 PM PDT

    For a long time, CPU's have had a big division between the front end ISA that runs machine code from the OS and user, and the microarchitecture that actually for does the low level math. So given that, how difficult is it to change out the front end ISA for a given uarch? I.e, could AMD slap an ARM ISA and decoder onto a zen uarch core? Or could Samsung rework an exynos core with risc-v Isa on top? Or could a cpu handle multiple ISA's depending on what it gets fed?

    submitted by /u/yokem55
    [link] [comments]

    Chip Challenges At 3/2nm (Semiconductor Engineering)

    Posted: 15 Sep 2020 12:27 AM PDT

    El Cheapo PSU Roundup

    Posted: 14 Sep 2020 10:40 AM PDT

    Five dirt cheap power supplies are tested by Hardware Busters. It is nice to have reviews of some highly affordable PSUs that no one ever bothers to test. Price range from 15 ($18) to 35 ($41.5) euros! This is episode one, so more are on the way.

    https://youtu.be/BIpag-FUrrk

    submitted by /u/crmaris
    [link] [comments]

    NVIDIA and Arm to Create World-Class AI Research Center in Cambridge

    Posted: 14 Sep 2020 10:14 AM PDT

    Indistinguishable From Magic: Manufacturing Modern Computer Chips (2012)

    Posted: 14 Sep 2020 12:49 PM PDT

    Is RTX Finally Worth it? DLSS + Ray Tracing Analysis

    Posted: 14 Sep 2020 05:47 AM PDT

    Benefits of multi-cycle cadence for SIMD?

    Posted: 14 Sep 2020 10:02 AM PDT

    GCN executes 64-wide waves on 16-wide SIMDs over 4 cycles. Seemingly, this arrangement will increase the dependent issue latency by 3 cycles vs executing on a 64-wide SIMD.

    I know AMD isn't stupid and there must be some benefit to this arrangement, but I can't think of any. Could someone please enlighten me?

    submitted by /u/FlamingFennec
    [link] [comments]

    Asus ROG Swift PG259QN Review: Hitting 360Hz

    Posted: 15 Sep 2020 03:04 AM PDT

    Intel's Wi-Fi 6E AX210 network adapter was certified by the Wi-Fi Alliance early August

    Posted: 14 Sep 2020 05:14 AM PDT
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