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    Home Unlabelled Hardware support: [Tom's Hardware] - AMD CTO Mark Papermaster: More Cores Coming in the 'Era of a Slowed Moore's Law'

    Hardware support: [Tom's Hardware] - AMD CTO Mark Papermaster: More Cores Coming in the 'Era of a Slowed Moore's Law'

    December 06, 2019

    Hardware support: [Tom's Hardware] - AMD CTO Mark Papermaster: More Cores Coming in the 'Era of a Slowed Moore's Law'

    [Tom's Hardware] - AMD CTO Mark Papermaster: More Cores Coming in the 'Era of a Slowed Moore's Law'

    Posted: 05 Dec 2019 03:27 PM PST

    Apple’s Activation Lock Will Make It Very Difficult to Refurbish Macs

    Posted: 05 Dec 2019 06:55 AM PST

    The Dark Side of Electronic Waste Recycling

    Posted: 05 Dec 2019 05:10 AM PST

    Western Digital Starts Sales of WD_Black P50 USB 3.2 Gen 2x2 SSDs

    Posted: 05 Dec 2019 02:19 PM PST

    Using FPGAs For AI

    Posted: 05 Dec 2019 12:37 PM PST

    Snapdragon XR2 Chip to Enable Standalone Headsets with 3K*3K Resolution & 7 Cameras

    Posted: 06 Dec 2019 01:59 AM PST

    [Actually Hardcore Overclocking] mobo PCB Breakdown: Gigabyte TRX40 Aorus Pro Wifi // the cheapest TRX40 board

    Posted: 05 Dec 2019 09:10 AM PST

    Does 5G on phone benefit 4G reception/handling? or might it negatively impact interference and battery life?

    Posted: 06 Dec 2019 12:43 AM PST

    In the places I live I don't expect to see 5G rolled out substantially for at least 2-3 years. Since I plan to change phone once or twice before it does, I wonder If getting a device that is purposefully not 5G could be a better choice?

    Is there anyway 5G tech benefits 4G?
    Is there any possibility that having unused 5G won't negatively impact battery life?

    submitted by /u/unsubstantiation
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    Apple is killing the charging plug on its highest-end phones by 2021, top analyst predicts

    Posted: 05 Dec 2019 03:26 PM PST

    Instructions per cycle: AMD Zen 2 versus Intel

    Posted: 05 Dec 2019 11:31 PM PST

    Could we get more bandwidth out of memory by routing pins to each individual stacked die in a RAM chip?

    Posted: 05 Dec 2019 08:28 PM PST

    Modern high capacity RAM chips are made of stacks of RAM dies all connected to the pins on the bottom, right? And I'm assuming that since the pin count for a one-layer RAM chip is about the same as (for example) a four or eight layer RAM chip, the higher capacity a RAM chip is, the more time it takes to fill it up with data, assuming saturation of the data pins' bandwidth.

    However, RAM chips on a DIMM or channel is striped together, and different channels are striped together, so would it be possible to also stripe the internal silicon layers of each RAM chip by connecting each of them individually?

    Applications can include cases where you don't need a lot of RAM (more than what fitting HBM on the processor will get you but less than a traditional 8-channel memory setup with DIMMs), but you need it to be fast. I feel that this would also work in mobile or embedded devices that need to be high performance, since you can just define a channel not as a set of RAM chips themselves, but as a set of silicon dies in the chips, allowing for more channels than would normally be allowed with the number of chips. Seeing how there isn't a lot of space in these devices and RAM tends to take up a lot of it, I feel that it would be helpful.

    Could this work in a current or future DDR revision or is it just impractical or impossible?

    submitted by /u/AgreeableLandscape3
    [link] [comments]

    Is Arm ready for server dominance?

    Posted: 05 Dec 2019 12:54 PM PST

    Measuring Reorder Buffer Capacity

    Posted: 05 Dec 2019 12:20 PM PST
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