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    Tuesday, January 14, 2020

    Home Unlabelled Hardware support: US finally prohibits ISPs from charging for routers they don’t provide

    Hardware support: US finally prohibits ISPs from charging for routers they don’t provide

    January 14, 2020

    Hardware support: US finally prohibits ISPs from charging for routers they don’t provide

    US finally prohibits ISPs from charging for routers they don’t provide

    Posted: 13 Jan 2020 04:35 PM PST

    (Anandtech) Here's Some DDR5-4800: Hands-On First Look at Next Gen DRAM

    Posted: 13 Jan 2020 03:08 PM PST

    I Ran Off with Intel’s Tiger Lake Wafer. Who Wants a Die Shot?

    Posted: 13 Jan 2020 08:32 AM PST

    Hundreds of millions of cable modems are vulnerable to new Cable Haunt vulnerability

    Posted: 13 Jan 2020 04:15 PM PST

    TRX80 and WRX80 Don’t Exist: Neither Does the ‘Intel LGA1159’ Socket

    Posted: 13 Jan 2020 02:26 PM PST

    Looking At The Linux Performance Two Years After Spectre / Meltdown Mitigations

    Posted: 13 Jan 2020 01:12 PM PST

    Lian Li 011D Mini teardown

    Posted: 13 Jan 2020 06:11 AM PST

    Deep Dive: 120 Hz Fluid Display – the best you’ll lay eyes on in 2020 - OnePlus

    Posted: 13 Jan 2020 07:08 AM PST

    DOD EksoBionics EKSO GT Exoskeleton

    Posted: 13 Jan 2020 09:02 PM PST

    Fake Chips? | Deep dive into very nerdy world of DIP IC counterfeiting, recycling, and remaking

    Posted: 13 Jan 2020 08:35 PM PST

    [VideoCardz] Intel preparing 22-core Intel Core i9-10990XE?

    Posted: 13 Jan 2020 08:30 AM PST

    Final parameters of 2D scaling

    Posted: 13 Jan 2020 11:46 AM PST

    TL;DR What are the physical, or economic limits to transistor scaling?

    We are getting close to the point where there are physical limitations to fabrication. The cost of chip manufacturing and design is growing exponentially. Chip fabs are now constantly talking about ideas such as 3D stacking to try to deal with the issue that transistor scaling will soon end.

    I am curious, what are the limits for each parameter? For example, 5nm as a limit to fin width. Currently TSMC "7nm" has lowest level interconnect width as 24nm and gate width as 36nm I believe. What is the physical limits to these parameters? I am aware you can make an atomic transistor in an academic lab, but my question is for mass manufactured chips.

    What node do you all think would be the last to offer a leap in density scaling?

    submitted by /u/Farrokh_Tir
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    Responding to the RAM OC and topology questions on the Hardware Uboxed 4x4GB vs 2x8GB video

    Posted: 13 Jan 2020 02:47 PM PST

    Enmotus MiDrive: PerformanceAND Price on One SSD

    Posted: 13 Jan 2020 12:19 PM PST

    The T-FORCE Delta Max 500GB SSD RGB-enabled Review

    Posted: 13 Jan 2020 08:38 AM PST

    ASRock to Launch Hyper Quad M.2 PCIe 4.0 Expansion Card

    Posted: 13 Jan 2020 12:58 PM PST

    A question about High Density Libraries/high power library

    Posted: 13 Jan 2020 05:31 AM PST

    When reading about TSMCs 7nm process i came across some terms like High density libraries and high power libraries

    Also i read that AMDs first gen ryzen was built on Glo Fos 14 nm low power plus LPP library/node

    can someone explain what these mean, in an easy to understand (+examples if you can) way

    submitted by /u/Ashraf_mahdy
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    Any tech reviews website that include benchmarks of CPUs above 720p, 1080p, low settings?

    Posted: 13 Jan 2020 10:05 AM PST

    I would love to see a real world scenarios where they compare how CPUs perform under GPU load, high/ultra settings, 1440p, 4K, etc., so I get a more realistic idea since most people including me who buy high-end gaming CPUs play above 720p, low settings except a few competitive titles maybe...

    So are there any tech reviews who do this?

    submitted by /u/HatefulAbandon
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